The SDR-LW 4940 is a high-performance multi-channel software radio device that supports open-source SDR design processes such as C/C++ and GNU Radio, as well as LabVIEW FPGAs, and is an ideal prototype for designing and deploying next-generation wireless systems to build a range of advanced research applications. Like all USRP devices, this device is powered by open-source, cross-platform UHD, which supports most applications and SDR frameworks such as GNU Radio.
SDR-LW 4940
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500GB SSD, 32GB RAM
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Frequency range of 1MHz-7.2GHz (tunable up to 8GHz)
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Supports 4 transmitters and 4 receivers, with an instantaneous bandwidth of up to 400MHz for each channel.
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Built-in Xilinx Zynq Ultrascale+ ZU28DR RFSoC
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Quad-core ARM Cortex-A53 CPU up to 1.2GHz
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Two FPGA programmable GPIO interfaces (HDMI)
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USB 3.0 interface
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QSFP28 port
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JTAG interface
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Support for external clock reference and PPS time reference
Product introduction
Technical parameter
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| Transmission | Reception | ||
| Channel Count | 4 | Channel Count | 4 |
| Frequency Range | 1MHz-7.2GHz, tunable to 8GHz | Frequency Range | 1MHz-7.2GHz, tunable to 8GHz |
| Frequency Step | Less than 1Hz | Frequency Step | Less than 1KHz |
| Max Output Power | Less than 23dBm | Max Input Power | Less than 20dBm |
| Gain Range | 60dB | Gain Range | ≤500 MHz 38dB ＞500 MHz 60dB |
| Gain Step | 1dB | Gain Step | 1dB |
| Max Real-Time Bandwidth | 400MHz | Max Real-Time Bandwidth | 400MHz |
| Average Noise | -146 dBm/Hz | Noise Figure | 500 MHz-3.1 GHz: 8dB 3.1 GHz-6 GHz: 6.5dB 6 GHz-8 GHz: 9dB |
| FPGA and Baseband | |||
| FPGA | Xilinx RFSoC XCUZ28DR | Processor | Intel i9-9900K |
| DRAM | 2 × 4 GB DDR4, 2.4 GT/s | Memory | 32G |
| GPIO | 2 HDMI | QSFP28 | 100Gbps or 4*10Gbps |
| ADC Resolution | 12 bits | RJ45 | 1Gbps*2 |
| DAC Resolution | 14 bits | Power | Max 200W |
| Operating Environment | |||
| Operating Temperature | 0-50℃ | Voltage | 12V |
| Humidity | 10%-90% (non-condensing) | Current | |